https://flagos-ai.github.io/FlagGems/optimization/Recent content in Backend Optimization on FlagGemsHugoenhttps://flagos-ai.github.io/FlagGems/optimization/ascend/Mon, 01 Jan 0001 00:00:00 +0000https://flagos-ai.github.io/FlagGems/optimization/ascend/<!-- Copyright 2026 FlagOS Contributors Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. --> <h1 id="ascend-optimization">Ascend optimization<a class="anchor" href="#ascend-optimization">#</a></h1> <h2 id="hardware-architecture">Hardware architecture<a class="anchor" href="#hardware-architecture">#</a></h2> <p>The Cube path executes matrix multiplication, the Vector path handles elementwise work and reductions, and the Scalar path handles address calculations and loop control. MTE engines move data from global memory (GM, usually HBM) into on-chip buffers. Cube uses L1, L0A, L0B, and L0C; Vector uses the Unified Buffer (UB). <strong>UB and L0 are distinct spaces; L1 is a Cube-side buffer, not the cross-core L2 cache.</strong> A kernel combining <code>tl.dot</code> with a Vector epilogue may need intermediate transfers and synchronization.</p>https://flagos-ai.github.io/FlagGems/optimization/hygon/Mon, 01 Jan 0001 00:00:00 +0000https://flagos-ai.github.io/FlagGems/optimization/hygon/<!-- Copyright 2026 FlagOS Contributors Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. --> <h1 id="hygon-optimization">Hygon optimization<a class="anchor" href="#hygon-optimization">#</a></h1> <p>Triton kernels run on Hygon DCUs through the HIP path. Tile sizes, warp counts, pipeline depth, and program ordering determine register, on-chip shared-memory (LDS), and cache use. This guide uses Hygon BW / <code>gfx936</code> to explain optimization mechanisms tied directly to those resources.</p>